Semiconductor modules are packaged in types of packages such as flat lead packages or flat leadless packages, such as P-TSLP packages or P-UFLGA packages. These types of package typically have no contacts extending through the package. Such packages, in particular the P-TSLP packages and the P-UFLGA packages, additionally have the disadvantage that external contact structures and flat leads are produced by complex etching processes, and wiring leads are created by etching down flat leads. Close tolerances are consequently not feasible and the co-planarity of the external structures is difficult to achieve. The low reproducibility when etching out external contact structures, and in particular when etching down wiring leads, causes an unacceptable reject rate in the fabrication of such components. Furthermore, a high degree of growth is observed in edge regions during the etching down.